PCI Express (PCIE) switch components are a new technology. For more information, see PCI Express Base Specification, Revision 1.1. The PCIE Specification describes a switch architecture, but there are few examples of PCIE switches in the marketplace. The PCIE Specification describes a “fixed” architecture for PCIE switches, with a fixed number of links at pre-determined widths.
FIG. 1 illustrates one embodiment of a PCIE topology. Computer system 100 includes a root complex (RC) 120, multiple endpoints 160, 170, 180, and 190, and switch 140. Root complex 120 denotes the root of an input/output (I/O) hierarchy that connects the microprocessor 110 and memory 130 subsystem to the I/O. As illustrated, root complex 120 supports one or more PCIE ports where each interface defines a separate hierarchy domain. Each hierarchy domain may be composed of a single endpoint 150 or a sub-hierarchy containing switch 140 and endpoints 160, 170, 180, and 190. Endpoint refers to a type of I/O device that can request or complete a transaction.
As used herein, the term upstream refers to a direction up the hierarchy of connection, e.g. towards root complex 120. The port on a switch that is closest topologically to the root complex is the upstream port. As an example, in FIG. 1, port 141 on switch 140 is an upstream port. Inversely, downstream, as used herein refers to a direction down the hierarchy of connection, e.g. away from root complex 120. The ports on a switch that are not the upstream port are downstream ports. In FIG. 1, ports 142, 144, 146, and 148 are downstream ports.
PCIE switch 140 provides the capability of a multi-drop bus in a PCIE hierarchy. On the upstream side of PCIE switch 140 is a single PCIE link. On the downstream side of PCIE switch 140 are one or more PCIE links.
Prior art switches have a pre-defined maximum width for the upstream PCIE connection and a fixed number of downstream PCIE connections. This limitation necessarily requires trade-offs not acceptable to all customers, or requires multiple separate components to satisfy the market requirements of all customers. For example, one customer might desire high fan-out connectivity and would value multiple downstream PCIE buses to satisfy a certain market requirement, while another customer might desire enhanced power management, and would not value multiple downstream PCIE buses, to satisfy a different market requirement. In order to satisfy multiple market requirements for switches, separate components are currently required.
If a component contains both a switch and an endpoint, the endpoint is placed (“hardwired”) in one of two places. For increased performance, an endpoint is attached directly to a PCIE root complex, using one of the connections available directly onto the root complex. For increased connectivity, an endpoint is attached further away from the root complex, downstream of a PCIE switch, thus keeping the high-bandwidth root complex connection available. A customer may require either one of these configurations, so separate components are currently required.